1. Field of the Invention
The present invention relates to the field of fabrication of semiconductor devices. More specifically, the invention relates to the fabrication of silicon-germanium semiconductor devices.
2. Background Art
In a heterojunction bipolar transistor, or HBT, a thin silicon-germanium layer is grown as the base of a bipolar transistor on a silicon wafer. The silicon-germanium HBT has significant advantages in speed, frequency response, and gain when compared to a conventional silicon bipolar transistor. Speed and frequency response can be compared by the cutoff frequency which, simply stated, is the frequency where the gain of a transistor is drastically reduced. Cutoff frequencies in excess of 100 Ghz have been achieved for the HBT, which are comparable to the more expensive GaAs. Previously, silicon-only devices have not been competitive for use where very high speed and frequency response are required.
The higher gain, speeds, and frequency response of the HBT have been achieved as a result of certain advantages of silicon-germanium not available with pure silicon, for example, narrower band gap, and reduced resistivity. Silicon-germanium may be epitaxially grown, however, on silicon wafers using conventional silicon processing and tools, and allows one to engineer device properties such as the band gap, energy band structure, and mobilities. For example, it is known in the art that grading the concentration of germanium in the silicon-germanium base builds into the HBT device an electric field, which accelerates the carriers across the base, thereby increasing the speed of the HBT device compared to a silicon-only device. One method for fabricating silicon and silicon-germanium devices is by chemical vapor deposition (xe2x80x9cCVDxe2x80x9d). A reduced pressure chemical vapor deposition technique, or RPCVD, used to fabricate the HBT device allows for a controlled grading of germanium concentration across the base layer. As already noted, speeds in the range of approximately 100 GHz have been demonstrated for silicon-germanium devices, such as the HBT.
Because the benefits of a high gain and high speed silicon-germanium HBT device can be either partially or completely negated by high base and emitter contact resistance, it is important that the resistance of the base and emitter contacts be kept low. In addition to the contact resistances, the geometry of the base and emitter regions may also affect the base and emitter resistance. For example, contact to the emitter has previously been made in a manner known in the art by designing an emitter which is xe2x80x9crouted outxe2x80x9d and whose width is increased to provide a satisfactory area in which to form an emitter contact. The geometry of the base region may necessitate providing a low resistance electrical pathway through a portion of the base itself between the base contact and the base-emitter junction. In order to provide lower resistance from the base contact to the base-emitter junction, the extrinsic base region is heavily doped by implantation (also called extrinsic doping). The heavily doped extrinsic base region has a reduced resistance.
The region in the base between the edge of the heavily doped extrinsic base region and the edge of the base-emitter junction is referred to as the link base region. The link base region adds a significant amount of resistance between the base contact and the base-emitter junction. It is, therefore, important for the reasons stated above that resistance of the link base region also be kept low. The resistance of the link base region is affected by the length of the link base region from the heavily doped extrinsic base region to the edge of the base-emitter junction. Since the base-emitter junction is substantially coterminous with an xe2x80x9cintrinsic base region,xe2x80x9d the link base region spans a distance between the intrinsic base region and the extrinsic base region. In other words, the link base region xe2x80x9clinksxe2x80x9d the extrinsic base region to the intrinsic base region.
The length of the link base region spanning from the heavily doped extrinsic base region to the intrinsic base region must be no smaller than a certain minimum separation distance in order to provide separation between the heavily doped region of the extrinsic base and the heavily doped region of the emitter near the base-emitter junction. The link base region itself is relatively lightly doped. If the separation between the heavily doped region of the extrinsic base and the heavily doped region of the emitter near the base-emitter junction is not greater than a minimum separation distance, the two heavily doped regions can form a high electric field junction and increase the leakage current between the emitter and the base, thereby degrading the performance characteristics of the HBT device.
Depending on the alignment of the sequence of steps in the fabrication process used to form the link base region, the intrinsic base region, the base-emitter junction, and to implant the heavily doped extrinsic base region, the distance across the link base region to the intrinsic base region can vary, often unpredictably. The distance across the link base region to the intrinsic base region is also referred to as the length of the link base region in the present application.
With perfect alignment of the sequence of steps in the fabrication process, the distance across the link base region can be minimized to the minimum separation distance just discussed. In that case, the link base resistance would also be minimized. In a fabrication process which uses two separate photomasks, for example, to form the link base region, the intrinsic base region, the base-emitter junction, and to implant the heavily doped extrinsic base region, there is always a margin of error in the alignment of the two photomask steps. Accounting for the misalignment of the two photomask steps in the fabrication process forces the fabrication of a much greater distance across the link base region than the minimum separation distance. Thus, the link base resistance is greater than the minimum possible link base resistance.
Other fabrication processes and tools have been tried in attempts to solve the problem of aligning the link base and extrinsic base to the emitter in silicon-germanium devices. One approach requires the use of selective epitaxy along with use of an inside spacer. Selective epitaxy presents a problem in that it is not currently used in high volume production of semiconductor devices. Selective epitaxy presents another problem in that selective epitaxial deposition occurs only on silicon regions and not on oxide regions. Since most process monitoring is done on oxide regions, selective epitaxy results in a substantial loss of process monitoring capability. Use of an inside spacer presents a further problem in that variability of emitter width is greater than with other methods, so some accuracy in control of emitter width is lost.
It is important to provide low resistances in the base and emitter contacts, the heavily doped extrinsic base region, and the link base region in order to improve the performance and operating characteristics of the HBT or other similar device such as a conventional bipolar transistor. Because the resistances of the base contact, the heavily doped extrinsic base region, and the link base region are in series, the reduction of any one of them will provide an improvement in the resistance of the conduction path from the base contact to the intrinsic base region of the HBT or base of other similar device. In addition, as feature sizes of bipolar devices are reduced, it is important to achieve accurate control over the size of certain features, such as the emitter width of the HBT. Furthermore, as feature size of CMOS devices is reduced it is important to achieve a concomitant reduction of feature size in bipolar devices on the same chip as CMOS devices.
Thus, there is need in the art to reduce the link base resistance by providing a fabrication process which does not rely on the alignment of separate photomasks to form the link base region, the intrinsic base region, the base-emitter junction, and to implant the heavily doped extrinsic base region. There is also need in the art for fabrication of a low link base resistance structure which achieves accurate control over the emitter width. There is a further need in the art for a fabrication process for bipolar devices which is scalable to the size of MOS and CMOS devices.
The present invention is directed to a method for fabricating a self-aligned emitter in a bipolar transistor. The invention overcomes need in the art for fabrication of a low link base resistance structure which achieves accurate control over the emitter width. The invention reduces the link base resistance of a bipolar transistor by providing a fabrication process which does not rely on the alignment of separate photomasks to form the link base region, the intrinsic base region, the base-emitter junction, and to implant the heavily doped extrinsic base region. The invention also provides a fabrication process for bipolar devices which is scalable to the size of MOS and CMOS devices.
According to the invention a silicon-germanium base is formed, which includes an extrinsic base region, a link base region, and an intrinsic base region. An etch stop layer, which for example can be silicon oxide, is deposited over the silicon-germanium base. A layer of polycrystalline silicon is then formed on the etch stop layer above the silicon-germanium base. The polycrystalline silicon layer is patterned to form a temporary emitter. The link base regions can be implant doped after fabricating the temporary emitter, for example, to reduce the resistance of the link base regions, i.e. the emitter and link base regions are self-aligned.
Link spacers are then fabricated on the sides of the temporary emitter. The link spacers can be formed, for example, by depositing a conformal layer of silicon oxide over the temporary emitter and then etching back the conformal layer. The length of the link base regions, which are below the spacers, can be determined by the deposition thickness of the conformal layer. The extrinsic base regions are implant doped after fabricating the link spacers, i.e. the emitter and extrinsic base regions are self-aligned.
The temporary emitter is then etched away and the etch stop layer is removed, forming a cavity between the link spacers. For example, a protective layer of silicon oxide can be deposited over the extrinsic base regions, link spacers and temporary emitter prior to patterning the temporary emitter and link spacers by opening a photoresist mask. A final emitter is then formed in the cavity. For example, the final emitter can be formed by depositing polycrystalline silicon in the cavity and forming an base-emitter junction within the intrinsic base region.